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Times back information was brought to new processor Design to AMDs to the public. So far this was acted under the code name “Barcelona”, this name applies like now admits became however only to the Quad core Opterons to servers. This Opterons is based on the “K10” - architecture, which was called in former times “K8L”. On the same architecture also the CCUs for Desktop computers of “star” (2 cores) and “Cities” become (4 cores) as well as “Hawk” and the Notebook CCU “Griffin” (of 2 cores, at the beginning of of 2008) to be based.

The memory controller with the K10-Architektur gets along with DD2-RAM with up to 667 MHz. The Prefetch Buffer, which becomes active, if data and instructions are requested, seizes 32 byte. Three speed Cache architecture consists large L1-Caches of the 128 KByte and the 512 KByte large L2-Caches. Both of L1 and L2-Cache each core possesses a its own. All cores together access 2 MByte a large L3-Cache.
The controller can access all 3 kinds of Caches and transfer also data of the L1-Cache into another. A detour over L3 and L2-Cache must be made.
Apart from new memory architecture are also the 128 bits long SSE units with just as broad bus for speed increases to provide. AMD promises more achievement in the comparison to the present Opteron and on average an improvement with Geiltkommaanwendungen up to 80 per cent by 40 per cent.
The capacity is to be reduced among other things by switching whole cores off. The clocks of the cores could be adjusted over the Bios. With single Thread applications the individual current core can run when desired clearly more highly clocked. AMD gives here no recommendations and leaves this Tuning possibility to the Main board manufacturers.
These will have to block two supply voltages for new architecture if it the switching off feature to support to want. The base becomes in this case then “AM2+” is called. Who knows still the old AM2-Sockel used also the new, in 65 Nm-proceeds manufactured CCUs to use. These use then however about 10 per cent more river. The publication date for the new technology is further quite spongelike indicated as “in the middle of 2007”.